PYJ-Dynasty Venture Fund

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  PYJ-Dynasty's key investment strategy is to identify qualified overseas returnees for starting up new ventures in China. We provide the founders with unique value-adds at different stages of a venture to enable successful launch and sustainable growth. Our Partners and Advisors are world renowned domain experts with proven track-records in technology development, venture investment, business management, as well as academic research. PYJ has developed an extensive network in both the US and China to source high quality deals.  

Prof. C. Patrick Yue


Patrick has 15 years of combined experience in academia and the semiconductor industry. His technical expertise and research interests are in the areas of CMOS RF and high-speed IC design, device and passive modeling, and CAD methodology for high-frequency analog ICs. He received his Ph.D. and M.S. degrees in EE from Stanford University in 1998 and 1994, respectively.

Since 2006, Prof. Yue has been an Associate Professor at UC Santa Barbara in the Department of Electrical and Computer Engineering. He is currently the Associate Director for the Computer Engineering Program. Prior to joining UCSB, he was an Assistant Professor in the ECE Department at Carnegie Mellon University from 2003 to 2006. Prof. Yue is an active consultant and an angel investor to a number of US and China-based hi-tech startup companies. He is currently a Board Member of BMTPow and a Board Observer of AltoBeam and Silicon Vox. He also serves on the Technical Advisory Board of AltoBeam, Accel Semiconductor, Mobim Technologies, Triductor Technology and Siliconaire.

Before entering academia, he co-founded Atheros Communications (NASDAQ: ATHR) in 1998, where he worked for four years and was a core member of the team that delivered the world's first single-chip RFIC based on standard digital CMOS processes for the IEEE 802.11 WLAN standard. Atheros' products are widely regarded as the underpinning technology that enabled WiFi. After leaving Atheros, Prof. Yue joined another startup, Aeluros (acquired by Netlogic, NASDAQ: NETL), where he worked on signal integrity and component modeling for 10-Gbps I/O interface circuits based on CMOS technology. While working full time in the industry, Prof. Yue served as a Consulting Assistant Professor in Stanford University's EE Department. In this role, he supervised doctoral candidates on high-frequency circuit and device research projects. During his graduate study, Prof. Yue has held summer positions at Texas Instruments, Hewlett-Packard Lab, and Stanford University.

Prof. Yue has contributed to more than sixty peer-reviewed technical papers and two book chapters. He was the co-recipient of the 2003 ISSCC Best Student Paper Award for demonstrating the first on-chip standing-wave clock distribution circuit. His 1998 paper "On-chip spiral inductors with patterned ground shields for Si-based RF IC's" is among the all-time most cited articles in the IEEE Journal of Solid-State Circuits according Thomson ISI. He currently holds a dozen U.S. patents, most of which are employed in commercial products. He has served on the technical program committees of the IEEE RFIC Symposium (RFIC), IEEE Asian Solid-State Circuit Conference (A-SSCC), International Symposium on VLSI Design, Automation & Test (VLSI-DAT), IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), and IEEE Compound Semiconductor Integrated Circuits Symposium (CSICS). He is a member of the IEEE Electron Devices Society VLSI Technology and Circuits Committee and has been an IEEE Senior Member since 2005.


Ingredients for Success: Industry and Academe Connections | Valuable Guidance and Advantages
Experienced Team with Proven Track Record | Unparalleled Strategic Insight